Multi-phase buck DC converter

ABSTRACT

A multi-phase buck DC converter comprise a plurality of storage inductors, a plurality of low-side switches, a first input capacitor, a second input capacitor, a plurality of high-side switches and at least one clamping capacitor. The storage inductors are used to drive a load. The low-side switches are connected to the storage inductors; respectively. The second input capacitor is connected to the first input capacitor in series. The contact of the first input capacitor and the second input capacitor is connected to one storage inductor. A part of the high-side switches are connected in series. One end of each clamping capacitor is connected to any two high-side switches connected in series and the other end is connected to the storage inductors.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of China application serialNo. 201310293636.5, filed on Jul. 12, 2013. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosure relates to a converter and, more particularly, to a buckDC converter.

2. Description of the Related Art

In recent years, interleaved buck DC converters are developed to meetthe requirement of low output current ripple. The interleaved buck DCconverter includes several conventional buck DC converters which areconnected in parallel and output to a plurality of inductors withdifferent phases. The conductive loss is reduced by a plurality ofinductors for shunting current. Additionally, the output ripple currentis lowered via the interleaved switching.

If the interleaved buck DC converter is applied in the high step-downratio, the main disadvantage is that the active switch needs towithstand the high voltage of the input end when the active switch isturned off, and thus high voltage-resisting switch components should bechosen. In addition, since the step-down ratio of the interleaved buckDC converter buck is not high enough, the duty cycle of the activeswitch needs to operate at the critical situation of 0%.Consequentially, the additional switching loss of the active switch inthe interleaved buck DC converter is generated, and the currentconductive loss at the low-side switch is increased.

In addition, in order to reduce the conductive loss of each inductor,the interleaved buck DC converter should make the inductive current oneach phase current average. Thus, a current control circuit should beadded to each phase circuit, which makes the circuit complex andincrease the cost of the components.

BRIEF SUMMARY OF THE INVENTION

An N-phase buck DC converter for driving loads is provided where theN=2n and N is an even number greater than 4. The N-phase buck DCconverter comprise N storage inductors, N low-side switches, a firstinput capacitor, a second input capacitor, N high-side switches and N−2clamping capacitors. The N storage inductors are connected to the loadsand are divided into a first part storage inductor and a second partstorage inductor. The first part storage inductor includes the firststorage inductor to the (2n−1)^(th) storage inductor with an odd numbersof intervals, the second part storage inductor includes the secondstorage inductor to the 2n^(th) storage inductor with the an evennumbers of intervals. One side of each low-side switch is connected tothe N storage inductors, respectively. The second input capacitor isconnected to the first input capacitor in series. The contact of thefirst input capacitor and the second input capacitor is connected to thesecond storage inductor of the N storage inductors. The N high-sideswitches are divided into a first part high-side switch and a secondpart high-side switch, the first part high-side switch includes thefirst high-side switch to the (2n−1)^(th) high-side switch with an oddnumbers of intervals, the second part high-side switch includes thesecond high-side switch to the 2n^(th) high-side switch with an evennumbers of intervals. The (2n−1)^(th) high-side switch of the first parthigh-side switch is connected to the (2n−1)^(th) the storage inductor ofthe N storage inductors. N−2 clamping capacitors are divided in to afirst part clamping capacitor and a second part clamping capacitor, thefirst part clamping capacitor include a first clamping capacitor to a(2n−3)^(th) clamping capacitor with an odd numbers of intervals. Oneside of a k^(th) clamping capacitor is connected to the k^(th) high-sideswitch and the (k+2)^(th) high-side switch and the other side of thek^(th) clamping capacitor is connected to the k^(th) storage inductor ofthe N storage inductors, wherein k is an odd number between 1 and(2n−3). The second part clamping capacitor includes a second clampingcapacitor to a (2n−2)^(th) clamping capacitor with an even numbers ofintervals. One side of a j^(th) clamping capacitor is connected to thej^(th) high-side switch and the (j+2)^(th) high-side switch and theother side of the j^(th) clamping capacitor is connected to the(j+2)^(th) storage inductor of the N storage inductors, wherein j is aneven number between 2 and (2n−2).

Another N-phase buck DC converter is provided and the N=2n+1 and N is anodd number greater than 3. The N-phase buck DC converter comprise Nstorage inductors, N low-side switches, a first input capacitor, asecond input capacitor, N high-side switches and N−2 clampingcapacitors. The N storage inductors are connected to the loads and aredivided into a first part and a second part. The first part includes thefirst storage inductor to the (2n+1)^(th) storage inductor with an oddnumbers of intervals, the second part includes the second storageinductor to the 2n^(th) storage inductor with the an even numbers ofintervals. One side of each low-side switch is connected to the Nstorage inductors, respectively. The second input capacitor is connectedto the first input capacitor in series. The contact of the first inputcapacitor and the second input capacitor is connected to the secondstorage inductor of the N storage inductors. The N high-side switchesare divided into a first part and a second part. The first part includesthe first high-side switch to the (2n+1)^(th) high-side switch with anodd numbers of intervals, the second part includes the second high-sideswitch to the 2n^(th) high-side switch with an even numbers ofintervals. The (2n−1)^(th) high-side switch of the first part isconnected to the (2n+1)^(th) the storage inductor of the N storageinductors. N−2 clamping capacitors are divided in to a first part and asecond part, the first part clamping capacitor include a first clampingcapacitor to a (2n−1)^(th) clamping capacitor with an odd numbers ofintervals. One side of a k^(th) clamping capacitor is connected to thek^(th) high-side switch and the (k+2)^(th) high-side switch and theother side of the k^(th) clamping capacitor is connected to the k^(th)storage inductor of the N storage inductors, wherein k is an odd numberbetween 1 and (2n−1). When N>3, the second part clamping capacitorincludes a second clamping capacitor to a (2n−2)^(th) clamping capacitorwith an even numbers of intervals. One side of a jth clamping capacitoris connected to the jth high-side switch and the (j+2)^(th) high-sideswitch and the other side of the jth clamping capacitor is connected tothe (j+2)^(th) storage inductor of the N storage inductors, wherein j isan even number between 2 and (2n−2).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a three-phase buck DC converter inan embodiment.

FIG. 2 is a schematic diagram showing a four-phase buck DC converter inan embodiment.

FIG. 3 is a sequence diagram of switching signals of the four-phase buckDC converter shown in FIG. 2.

FIG. 4 is a schematic diagram showing the equivalent circuit of thefour-phase buck DC converter in a period of t₀≦t≦t₁.

FIG. 5 is a schematic diagram showing the equivalent circuit of thefour-phase buck DCX converter in periods of t₁≦t≦t₂, t₃≦t≦t₄, t₅≦t≦t₆and t₇≦t≦t₈.

FIG. 6 is the equivalent circuit of the four-phase buck DC converter inthe period of t2≦t≦t3.

FIG. 7 is the equivalent circuit of the four-phase buck DC converter inthe period of t4≦t≦t5.

FIG. 8 is the equivalent circuit of the four-phase buck DC converter inthe period of t₆≦t≦t₇.

FIG. 9 is a schematic diagram showing a N-phase buck DC converter.

FIG. 10 is a sequence diagram showing switch signals at the high-side ofthe N-phase buck DC converter.

FIG. 11 is a sequence diagram showing switch signals at the low-side ofthe N-phase buck DC converter.

FIG. 12 to FIG. 16 are schematic diagrams showing waveforms of thesignal simulation results of the four-phase buck DC converter in FIG. 2.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A multi-phase buck DC converter is provided. A plurality of inputcapacitors and clamping capacitors are separately set at a plurality ofconverter circuits with different phases, so as to replace aconventional single input capacitor component with high capacitance.Thus, the cost of the capacitors is reduced, the step-down ratio can beincreased via split-phases, and the voltage across the high side and thelow side is decreased. The detail descriptions of the abovedisadvantages would be illustrated in the following embodiments.

The multi-phase buck DC converter with different phases can be chosenaccording to the specification (the value of the voltage or the currentneeded to be converted) and the cost. The multi-phase buck DC converterswith different phases are illustrated in the following embodiments.

FIG. 1 is a schematic diagram showing a three-phase buck DC converter100 in an embodiment. The three-phase buck DC converter 100 includes afirst input capacitor C₁, a second input capacitor C₂, a first clampingcapacitor C_(C1), a first high-side switch S₁, a second high-side switchS₂, a third high-side switch S₃, a first low-side switch S_(D1), asecond low-side switch S_(D2), a third low-side switch S_(D3), a firststorage inductor L₁, a second storage inductor L₂, a third storageinductor L₃ and an output capacitor C_(O).

The first input capacitor C₁ and the second input capacitor C₂ in thethree-phase buck DC converter 100 are connected in series to receive theinput voltage V_(in), so as to stabilize the voltage and decrease thecut-off voltage stress of the switching component in the three-phasebuck DC converter 100. The contact of the first input capacitor C₁ andthe second input capacitor C₂ is connected to the second storageinductors L₂. The input voltage V_(in) of the three-phase buck DCconverter 100 is approximately equally distributed on the first inputcapacitor C₁ and the second input capacitor C₂. The first high-sideswitch S₁, the second high-side switch S₂ and the third high-side switchS₃ can be divided into a first pan (the first high-side switch S₁ andthe third high-side switch S₃) and a second part (the second high-sideswitch S₂). In the first part, the first high-side switch S₁ and thethird high-side switch S₃ are connected in series, the first high-sideswitch S₁ at the front end is connected to the first input capacitor C₁,the third high-side switch S₃ at the back end is connected to the thirdstorage inductor L₃, the contact of the first high-side switch S₁ andthe third high-side switch S₃ is connected to the first storageinductors L₁ via a first clamping capacitor C_(C1).

On the other side, one end of the second high-side switch S₂ in thesecond part is connected to the second input capacitor C₂, and the otherend is connected to the first low-side switch S_(D1), the secondlow-side switch S_(D2) and the third low-side switch S_(D3). The firstlow-side switch S_(D1), the second low-side switch S_(D2) and the thirdlow-side switch S_(D3) are correspondingly connected to the firststorage inductor L₁, the second storage inductor L₂ and the thirdstorage inductor L₃, respectively. One end of the output capacitor C_(O)is connected to the first low-side switch S_(D1), the second low-sideswitch S_(D2) and the third low-side switch S_(D3), and the other sideis connected to the first storage inductor L₁, the second storageinductor L₂ and the third storage inductor L₃. In addition, the resistorR is connected to the output capacitor C_(O) in parallel.

In the above embodiment, the three-phase buck DC converter 100 isprovided, but the buck DC converter is not limited to three phases, thesetting manner of the four phases and N phases buck DC converters areprovided in the following embodiments, wherein N is any positive integermore than 3. FIG. 2 is a schematic diagram showing a four-phase buck DCconverter in an embodiment.

In FIG. 2, the four-phase buck DC converter 200 includes a first inputcapacitor C₁, a second input capacitor C₂, a first clamping capacitorC_(C1) and a second clamping capacitor C_(C2), a first high-side switchS₁, a second high-side switch S₂, a third high-side switch S₃, a fourthhigh-side switch S₄, a first low-side switch S_(D1), a second low-sideswitch S_(D2), a third low-side switch S_(D3), a fourth low-side switchS_(D4), a first storage inductor L₁, a second storage inductor L₂, athird storage inductor L₃, a fourth storage inductor L₄ and an outputcapacitor C_(O). The high-side switches are divided into a first part(the first high-side switch St and the third high-side switch S₃) and asecond part (the second high-side switch S₂ and the fourth high-sideswitch S₄).

In the four-phase buck DC converter 200, the first input capacitor C₁and the second input capacitor C₂ are connected in series, and thecontact of the two input capacitors is connected to the second storageinductor L₂.

In the first part of the high-side switches, the first high-side switchS₁ and the third high-side switch S₃ are connected in series, the firsthigh-side switch S₁ is connected to the first input capacitor C₁, thethird high-side switch S₃ is connected to the third storage inductor L₃,the contact of the first high-side switch S₁ and the third high-sideswitch S₃ is connected to the first storage inductor L₁ via the firstclamping capacitor C_(C1).

On the other side, in the second part of the high-side switches, thesecond high-side switch S₂ and the fourth high-side switch S₄ areconnected in series, the second high-side switch S₂ is connected to thesecond input capacitor C₂. One end of the fourth high-side switch S₄ isconnected to a resistor R and the other end of the output capacitorC_(O) (that is a negative end of the output signal). The contact of thefourth high-side switch S₄ and the second high-side switch S₂ isconnected to the corresponding fourth storage inductor L₄ via the secondclamping capacitor C_(C2).

One side of each low-side switch S_(D1), S_(D2), S_(D3) and S_(D4) isconnected to the corresponding storage inductor L₁, L₂, L₃ and L₄,respectively. The other side of each low-side switch S_(D1), S_(D2),S_(D3), and S_(D4) is connected to one side of the fourth high-sideswitch S₄. The two sides of the output capacitor C_(O) are respectivelyconnected to the low-side switches S_(D1), S_(D2), S_(D3) and S_(D4) andthe storage inductors L₁, L₂, L₃ and L₄. In addition, the resistor R andthe output capacitor C_(O) are connected in parallel.

In order to explain the circuit of the disclosure more clearly, thefour-phase buck DC converter 200 in FIG. 2 is taken as an example toexplain the operation mode. Please refer to FIG. 3. FIG. 3 is a sequencediagram of switching signals of the four-phase buck DC converter shownin FIG. 2.

Please refer to FIG. 4; FIG. 4 is a schematic diagram showing theequivalent circuit of the four-phase buck DC converter in a period oft₀≦t≦t₁. In the embodiment in FIG. 3 and FIG. 4, the loop operation ofthe four-phase buck DC converter 200 has been stabilized, it is not theinitial startup state, and the time point t₀ does not represent thetiming of the initial startup.

As shown in FIG. 3 and FIG. 4, the first high-side switch S₁ is turnedon, the other high-side switches S₂, S₃ and S₄ are turned off (therelating circuit of the turned off high-side switches S₂, S₃ and S₄ inFIG. 4 are represented by dotted lines), the first input capacitor C₁discharges power to the first storage inductor L₁ and the first clampingcapacitor C_(C1) to drive the load via the storage inductors L₁.

In the period of t₀≦t≦t₁, the voltage across the second clampingcapacitor C_(C2) is clamped to a fixed voltage, and the first inputcapacitor C₁ drives the load through the first storage inductor L₁. Theenergy storage of the second storage inductor L₂, the third storageinductor L₃, the fourth storage inductor L₄ is finished in the previousloop operation, and the second output capacitor C₂, the third outputcapacitor C₃ and the fourth output capacitor C₄ drive the load throughthe second storage inductor L₂, the third storage inductor L3 and thefourth storage inductor L₄.

Please refer to FIG. 5. FIG. 5 is a schematic diagram showing theequivalent circuit of the four-phase buck DC converter 200 in the periodof t₁≦t≦t₂, t₃≦t≦t₄, t₅≦t≦t₆ and t₇≦t≦t₈. That is, FIG. 5 is theequivalent circuit of the four-phase buck DC converter 200 in the periodof t_(k-1)≦t≦t_(k), wherein kε{2, 4, 6, 8}.

As shown in FIG. 3 and FIG. 5, the high-side switches S₁, S₂, S₃ and S₄are turned off in the four modes (the relating circuit of high-sideswitches S₁, S₂, S₃ and S₄ in FIG. 5 which are turned off arerepresented by dotted lines). In the period of t₁≦t≦t₂, t₃≦t≦t₄, t₅≦t≦t₆and t₇≦t≦t₈, the second clamping capacitor C_(C2) and the first clampingcapacitor C_(C1) are clamped to a fixed voltage respectively and drivethe load through the storage inductors L₁, L₂, L₃ and L₄.

FIG. 6 is the equivalent circuit of the four-phase buck DC converter 200in the period of t2≦t≦t3.

As shown in FIG. 3 and FIG. 6, the fourth high-side switch S4 is turnedon in the mode, the other high-side switches S₁, S₂ and S₃ are turnedoff (the relating circuit of the turned off high-side switches S₁, S₂and S₃ in FIG. 6 are represented by dotted lines), the second clampingcapacitor C_(C2) discharges to the fourth storage inductor L₄, anddrives the load through the fourth storage inductor L₄.

In the period of t2≦t≦t3, the voltage across the first clampingcapacitor C_(C1) is clamped to a fixed voltage, at the same time, thestorage inductors L₁, L₂ and L₃ drive the load and transmit the outputsignal to the load accordingly.

Please refer to FIG. 7, FIG. 7 is the equivalent circuit of thefour-phase buck DC converter 200 in the period of t₄≦t≦t₅. In the mode,the third high-side switch S₃ is turned on, the other high-side switchesS₁, S₂ and S₄ are turned off (the relating circuit of the turned offhigh-side switches S₁, S₂ and S₄ in FIG. 7 are represented by dottedlines), the first clamping capacitor C_(C1) discharges to the thirdstorage inductor L₃ and drives the load through the third storageinductor L₃.

In the period of t4≦t≦t5, the voltage across the second clampingcapacitor C_(C2) is clamped to a fixed voltage, at the same time, thestorage inductors L₁, L₂ and L₄ drive the load and transmit the outputsignal to the load accordingly.

Please refer to FIG. 8, FIG. 8 is the equivalent circuit of thefour-phase buck DC converter 200 in the period of t₆≦t≦t₇. In the mode,the third high-side switch S₂ is turned on, the other high-side switchesS₁, S₃ and S₄ are turned off (the relating circuit of the turned offhigh-side switches S₁, S₃ and S₄ in FIG. 8 are represented by dottedlines), the second input capacitor C₂ discharges to the second storageinductor L₂ and the second clamping capacitor C_(C2), and it drives theload through the second storage inductor L₂.

In the period of t₆≦t≦t₇, the voltage across the first clampingcapacitor C_(C1) is clamped to a fixed voltage, at the same time, thestorage inductors L₁, L₃ and L₄ drive the load and transmit the outputsignal to the load accordingly.

As shown in the above embodiments, in the periods of t₀≦t≦t₁, t₂≦t≦t₃,t₄≦t≦t₅ and t₆≦t≦t₇ (shown in FIG. 4, FIG. 6, FIG. 7 and FIG. 8), one ofthe high-side switches S₁, S₂, S₃ and S₄ are turned on one by one, oneinput capacitor charge one clamping capacitor, at the same time, theinput capacitor discharges to the corresponding storage inductor and theload (as shown in FIG. 4 and FIG. 8), or one clamping capacitor that hasbeen charged discharges to the corresponding storage inductor and theload (shown in FIG. 6 and FIG. 7).

In other words, the four-phase buck DC converter 200 includes fourcapacitors (the first input capacitor C₁, the second input capacitor C₂,the first clamping capacitor C_(C1) and the second clamping capacitorC_(C2)) which are responsible for the power supply of four phases(t₀≦t≦t₁, t₂≦t≦t₃, t₄≦t≦t₅ and t₆≦t≦t₇), respectively. The dischargetime of each capacitor is a quarter of the duty cycle (D).

The duty cycle (D) of the four-phase buck DC converter 200 is theproportion a full cycle deducting of t₁˜t₂, t₃˜t₄, t₅˜t₆ and t₇˜t₈ inthe period of t₀˜t₈, which can be expressed as:

$D = \frac{\left( {t_{1} - t_{0}} \right) + \left( {t_{3} - t_{2}} \right) + \left( {t_{5} - t_{4}} \right) + \left( {t_{7} - t_{6}} \right)}{t_{8} - t_{0}}$

Wherein the duty cycle (D) is between 0 and 1.

In the embodiment, the ratio of the output voltage (V_(O)) and the inputvoltage (V_(in)) of the four-phase buck DC converter 200 (that is, thestep-down ratio of the four-phase buck DC converter 200) can beapproximately expressed as:V _(o) /V _(in) =D/4

That is, except that the step-down ratio can be adjusted via the dutycycle (D), a more significant step-down effect can be got through thefour phases design of the four-phase buck DC converter 200. The outputvoltage of the four-phase buck DC converter 200 can be adjusted to aquarter of the original input voltage.

Thus, it does not need to overly dependent on reducing the duty cycle toachieve the step-down effect. That is, the four-phase buck DC converter200 can be operated at a long duty cycle (D). Thus, it does not need tosignificantly reduce the duty cycle to achieve a sufficient step-downratio, which can avoid unexpected actions of the switching componentsdue to the too low duty cycle.

In the four-phase buck DC converter 200, both the voltage V_(C1) of theinput capacitor C₁ and the voltage V_(C2) of the input capacitor C₂ arehalf of the input voltage Vin. Both the maximum clamping voltage of thevoltage V_(CC1) of the first clamping capacitor C_(C1) and the voltageV_(CC2) of the second clamping capacitor C_(C2) are a quarter of theinput voltage Vin.

In other words, the input capacitor C₁, the input capacitor C₂, thefirst clamping capacitor C_(C1) and the second clamping capacitor C_(C2)which are scattered only need to withstand a low voltage. The maximumcross voltage of the first clamping capacitor C_(C1) and the secondclamping capacitor C_(C2) in the embodiment is a quarter of the inputvoltage Vin.

At the same time, the maximum cross voltage of each high-side switch S₁,S₂, S₃ and S₄ are lowered to half of the input voltage Vin by adding thefirst clamping capacitor C_(C1) and the second clamping capacitorC_(C2), and the voltage of each low-side switch S_(D1), S_(D2), S_(D3)and S_(D4) can be lowered to a quarter of the input voltage Vin.

On the other hand, the average current of the inductive current i_(L1),i_(L2), i_(L3) and i_(L4) of the storage inductors L₁, L₂, L₃ and L₄ isa quarter of output current Io. As a result, the storage inductors L₁,L₂, L₃ and L₄ can be chosen from inductor components with lowerinductance value compared to the conventional circuit structure, and theripple effect of the output current Io can be reduced by an interleaveswitch of the four phases. In addition, the four-phase buck DC converter200 can automatically reach current-sharing in the four phases.

On the other hand, the detail operating principle of the three-phasebuck DC converter 100 in the FIG. 1 can refer to that of the four-phasebuck DC converter 200 in FIG. 4 to FIG. 8, which is omitted herein.

In the three-phase buck DC converter 100 in FIG. 1, the maximum crossvoltage of the high-side switches S₁, S₂ and S₃ can be lowered totwo-thirds of the input voltage Vin. The maximum cross voltage of eachlow-side switch S_(D1), S_(D2) and S_(D3) can be lowered to one-third ofthe input voltage Vin. The voltage V_(C1) of the first input capacitorC₁ and the voltage V_(C2) of the second input capacitor C₂ aretwo-thirds and one-third of the input voltage Vin, respectively. Thevoltage V_(CC1) of the first clamping capacitor C_(C1) is one-third ofthe input voltage Vin. The average current of the current i_(L1), i_(L2)and i_(L3) on the storage inductors L₁, L₂ and L₃ are all one-third ofthe average output current I_(o).

That is, the three-phase buck DC converter 100 in FIG. 1 can achieve thesimilar effect by setting the first input capacitor C₁, the second inputcapacitor C₂, the first clamping capacitor C_(C1) and the outputcapacitor C_(O).

In addition, the setting and operation of the three-phase buck DCconverter 100 and the four-phase buck DC converter 200 are provided inthe above embodiments, which is not limited herein, and the setting andthe operating principle of the buck DC converter with different phasescan be analogized according to the similar setting.

According to the three-phase buck DC converter and the four-phase buckDC converter, an N-phase buck DC converter is provided in the followingparagraphs, and N can be any positive integer greater than 3. Pleaserefer to FIG. 9. FIG. 9 is a schematic diagram showing an N-phase buckDC converter. In FIG. 9, the N-phase buck DC converter includes twoinput capacitors (the first input capacitor C₁ and the second inputcapacitor C₂), N−2 clamping capacitors (only four clamping capacitorsC_(C1), C_(C2), C_(C3), and C_(C2n-2) of the N−2 clamping capacitors areshown), N high-side switches S₁ . . . S_(2n), N low-side switchesS_(D1), . . . , S_(D2n), N storage inductors L₁, . . . , L_(2n) and anoutput capacitor C_(O). N is any positive integer that makes N=2n (N isan even number) or N=2n+1 (N is an odd number), which is defined bywhether N is even number or odd number, In order to be convenient forexplanation in FIG. 9, N is an even number and 2n=N, persons having theordinary skill in the art can infer the connection manner when N is anodd number (N=2n+1) according to FIG. 9.

In FIG. 9, the position of the four clamping capacitors C_(C1), C_(C2),C_(C3) and C_(C2n-2) is shown, and the others clamping capacitors areomitted. The N-phase buck DC converter 900 includes N−2 clampingcapacitors. The number of the clamping capacitor is depend on the totalnumber of the phases, the three-phase buck DC converter includes oneclamping capacitor, the four-phase buck DC converter includes twoclamping capacitors, and so on.

In the architecture, the first input capacitor C₁ and the second inputcapacitor C₂ are connected in series.

As shown in FIG. 9, the N storage inductors L₁ to L₂n are connected tothe loads. The N storage inductors are divided into a first part (asshown in the odd part circuit in the outline 901 in FIG. 9) and a secondpart (as shown in the odd part circuit in the outline 902 in FIG. 9),the first part storage inductor includes the first storage inductor L₁to the (2n−1)^(th) storage inductor L_(2n-1) with an odd number ofintervals, the second part storage inductor includes the second storageinductor L₂ to the 2n^(th) storage inductors La with an even number ofintervals.

One end of the N low-side switches S_(D1) to S_(D2n) is connected to theN storage inductors L₁ to L_(2n), respectively.

The contact of the first input capacitor C₁ and the second inputcapacitor C₂ is connected to the second storage inductors L₂ of the Nstorage inductors.

The N high-side switches S₁ to S_(2n) are divided into a first part (asshown in the outline 901 in FIG. 9) and a second part (as shown in theoutline 902 in FIG. 9). The first part high-side switch includes thefirst high-side switch S₁, the third high-side switch S₃ . . . and the(2n−1)^(th) high-side switch S_(2n-1) with an odd number of intervals.The high-side switches S₁ to S_(2n-1) of the first part are connected inseries sequentially. One end of the first high-side switch (the firsthigh-side switches S₁) in the first part is connected to the first inputcapacitor C₁, the last high-side switch (the (2n−1)^(th) high-sideswitch S_(2n-1)) in the first part is connected to the (2n−1)^(th)storage inductor L_(2n-1).

The second part high-side switches includes the second high-side switchS₂, the fourth high-side switch S₄ . . . and the 2n^(th) high-sideswitch with an even number of intervals. The high-side switchesS₂˜S_(2n) of the second part are connected in series sequentially. Oneend the first high-side switch (the second high-side switch S₂) in thesecond part is connected to the second input capacitor C₂.

The N−2 clamping capacitors are divided in to a first part (as shown inthe outline 901 in FIG. 9) and a second part (as shown in the outline902 in FIG. 9). The second part clamping capacitor can be distinguishedwhen N>3. If N=3, the buck DC converter only includes one clampingcapacitor (the three-phase buck DC converter 100 in FIG. 1 includes oneclamping capacitor C_(C1)), and thus there is no second part clampingcapacitor. In the embodiment of FIG. 9, N>3.

The first part of the N−2 clamping capacitors includes the firstclamping capacitor C_(C1), the third clamping capacitor C_(C3), . . . ,and the (2n−3)^(th) clamping capacitor (not shown) with an odd number ofintervals. One side of the k^(th) clamping capacitor is connectedbetween the k^(th) high-side switch and the (k+2)^(th) high-side switch.The other side of the k^(th) clamping capacitor is connected to thek^(th) storage inductor of the N storage inductors, wherein k is an oddnumber between 1 and (2n−3). For example, one end of the first clampingcapacitor C_(C1) is connected between the first high-side switch St andthe third high-side switch S₃, and the other end of the first clampingcapacitor C_(C1) is connected to the first storage inductor L₁; one endof the third clamping capacitor C_(C3) is connected between the thirdhigh-side switch S₃ and the fifth high-side switch S₅, and the other endof the third clamping capacitor C_(C3) is connected to the third storageinductor L₃.

The second part of the N−2 first clamping capacitors includes the secondclamping capacitor C_(C2), the fourth clamping capacitor (not shown inthe figure) . . . to the (2n−2)^(th) clamping capacitor C_(C2n-2) witheven number of intervals. One side of the jth clamping capacitor isconnected between the jth high-side switch and the (j+2)^(th) high-sideswitch, the other side of the jth clamping capacitor is connected to the(j+2)^(th) storage inductor of the N storage inductors, and j is an evennumber between 2 and (2n−2). For example, one end of the second clampingcapacitor C_(C2) is connected to the second high-side switch S₂ and thefourth high-side switch S₄, and the other end of the second clampingcapacitor C_(C2) is connected to the fourth storage inductor L₄; one endof the (2n−2)^(th) clamping capacitor C_(C2n-2) is connected between the(2n−2)^(th) high-side switch (not shown in FIG. 9) and the 2n^(th)high-side switches S_(2n), the other end of the (2n−2)^(th) clampingcapacitor C_(C2n-2) is connected to the 2n^(th) storage inductor L_(2n).

One end of the output capacitor C_(O) is connected to the low-sideswitches Sot to S_(D2n), and the other end is connected to the storageinductors L₁ to L_(2n). In addition, the resistor R is connected to theoutput capacitor C_(O) in parallel.

FIG. 9 shows the general form of the N-phase buck DC converter 900. Thefour-phase buck DC converter 200 shown in the FIG. 2 is an example ofN=4(n=2). The three-phase buck DC converter 100 shown in the FIG. 1 isan example of N=3. The various implementations when N is a differentnumber can be inferred with referring to the FIG. 1, FIG. 2 and FIG. 9.

In the N-phase buck DC converter 900 in the FIG. 9, the relationshipbetween the on/off of the high/low-side switches and thecharge/discharge of the capacitors can refer to the related illustrationof the four-phase buck DC converter 200 in the previous embodiment (FIG.2 to FIG. 8). When the T^(th) high-side switches is turned on, the otherN−1 high-side switches are turned off, the corresponding T^(th) low-sideswitch is turned off and the other N−1 low-side switches are turned on.On the other hand, when the T^(th) high-side switch is turned on, oneinput capacitor charges one clamping capacitor via the T^(th) high-sideswitch and drives the load via one storage inductor, or one clampingcapacitor discharges and drives the load via one storage inductor. T isa positive integer between 1 and N. The detailed charging/dischargingmethod is omitted herein.

FIG. 10 is a sequence diagram showing switch signals at the high-side ofthe N-phase buck DC converter 900 in the FIG. 9. FIG. 11 is a sequencediagram showing switch signals at the low-side of the N-phase buck DCconverter 900 in the FIG. 9.

The switching signal of the interlacing N-phase buck DC converter isshown in FIG. 10, and V_(g1), V_(g2), V_(g3) to Vgn respectivelyrepresents the gate voltage signals of the high-side switches S₁ toS_(n), the phases of switches are interlaced, as shown in FIG. 10. Theinterval between the gate voltage signal V_(g1) and V_(g2) of thehigh-side switches S₁ and S₂ is 360/N degrees (120 degrees in thethree-phase buck DC converter, 90 degrees in the four-phase buck DCconverter, 72 degrees in the five-phase buck DC converter, and so on).The interval between the gate voltage signal V_(g2) and V_(g4) of thehigh-side switches S₂ and S₄ is 360/N degrees, The interval between thehigh-side switches S₄ and S₃, the high-side switches S₃ and S₅ are all360/N degrees, and so on. Consequentially, as shown in FIG. 10, thephases of the gate voltage signals of each switch are interlaced toreduce the ripple effect.

In addition, as shown in FIG. 11, V_(gD1), V_(gD2), V_(gD3) and V_(gDn)respectively represents the gate voltage signals of the low-sideswitches S_(D1) to S_(Dn), please refer to FIG. 10 and FIG. 11, thehigh-side switches and the low-side switches are switched incomplementary (the gate voltage signal V_(g1), V_(g2), V_(g3) to V_(gn)of the high-side and the gate voltage signal V_(gD1), V_(gD2), V_(gD3)to V_(gDn) of the low-side are complementary). In FIG. 11, the phases ofthe gate voltage signals V_(gD1), V_(gD2), V_(gD3) to V_(gDn) areinterlaced to reduce the ripple effect.

In addition, the N-phase buck DC converter 900 can achieveabove-mentioned effect by setting two input capacitors, N−2 clampingcapacitors and one output capacitor C_(O).

The signal simulation results of the multi-phase buck DC converter (thefour-phase buck DC converter 200 is taken as an example, which is notlimited) are provide in the following paragraphs to state the operatingcharacteristics of the buck DC converter. Please refer to FIG. 12 toFIG. 16, and FIG. 12 to FIG. 16 are schematic diagrams showing waveformsof the signal simulation results of the four-phase buck DC converter 200in the FIG. 2

In the signal simulations shown in FIG. 12 to FIG. 6, testspecifications are shown as follows: the input voltage V_(in) is 19V,the output voltage V_(o) is 1V, the output current I_(o) is 100 A, theswitching frequency is 350 kHz, the inductance of the storage inductorsL₁, L₂, L₃ and L₄ is 056 μH, the capacitance of the clamping capacitorC_(C1) and C_(C2) is 150 Mf/6.3V, the capacitance of the inputcapacitors C₁ and C₂ is 100 μF/10V, the capacitance of the outputcapacitor C_(O) is 560 μF/2.5V, the high-side switches S₁ to S₄ and thelow-side switches S_(D1) to S_(D4) are N type metal oxidesemiconductors, the Vds is 30V.

FIG. 12 shows the gate signal waveform of the high-side switches in thefour-phase buck DC converter 200. Under the same condition thatstep-down ratio is nineteen, the duty cycle of the four-phase buck DCconverter 200 is about 4/19=0.22 (the duty cycle of the conventionalconverter is about 1/19=0.055), and thus the four-phase buck DCconverter 200 can operate at a longer duty cycle, in other words, theturn-on time of the low-side switches is shortened to reduce thetransmission loss of the low-side switches.

FIG. 13 is a schematic diagram showing the cross voltage waveform of thehigh-side switches in the four-phase buck DC converter 200. Please referto the switching mode shown in the FIG. 3 to FIG. 8, the maximum crossvoltage V_(D1) of the high-side switch S₁ in the converter is 9.5V, themaximum cross voltage V_(D2) of the high-side switch S₂ is 4.75V, themaximum cross voltage V_(D3) of the high-side switch S₃ is 9.5V, themaximum cross voltage V_(D4) of the high-side switch S₄ is 9.5V (themaximum cross voltage of the high-side switch in a conventionalconverter is about 19V). Thus, compared to the conventional converter,the voltage of the high-side switches S₁, S₃ and S₄ can be lowered tohalf of the input voltage, the voltage of the high-side switches S₂ canbe lowered to a quarter of the input voltage, Thus, switch componentswith low voltage-resistor and low stray capacitance can be used toreduce the switching loss.

FIG. 14 is a schematic diagram showing the cross voltage waveform of thelow-side switches in the four-phase buck DC converter 200. Please referto the switching mode shown in the FIG. 3 to FIG. 8, the maximum crossvoltage of the low-side switches S_(D1), S_(D2), S_(D3) and S_(D4) inthe converter are about 4.75V. In contrast, the maximum cross voltage ofthe low-side switches in the conventional converter is about 19V. Thus,compared to the conventional converter, the voltage of the low-sideswitches S_(D1) to S_(D4) can be lowered to a quarter of the inputvoltage, Thus, switch components with low value of permissible voltageand low conducting resistance can be used to reduce the transmissionloss caused by the high current.

FIG. 15 is a schematic diagram showing the inductive current waveform ofthe four-phase buck DC converter 200 and the sum of the inductivecurrent waveform of the four-phase buck DC converter 200.

Without the control of current sharing, average values of the inductivecurrent I_(L1), I_(L2), L_(L3) and I_(L4) in the four-phase buck DCconverter 200 are almost the same. Please refer to the sum of theinductive current waveform of the four-phase buck DC converter 200, theripple current Δi_(o-new) of the converter is about 0.642 A (Incontrast, the ripple current of the conventional converter is about4.528 A). Thus, the converter can achieve a lower output ripple current.

FIG. 16 is a schematic diagram showing the output voltage and inductancecurrent waveform of the four-phase buck DC converter 200 when the loadcurrent of the four-phase buck DC converter 200 increases from 50 A to100 A. Whether the four-phase buck DC converter 200 is half load or fullload, it can make inductors have current sharing.

Although the present disclosure has been described in considerabledetail with reference to certain preferred embodiments thereof, thedisclosure is not for limiting the scope. Persons having ordinary skillin the art may make various modifications and changes without departingfrom the scope. Therefore, the scope of the appended claims should notbe limited to the description of the preferred embodiments describedabove.

What is claimed is:
 1. An N-phase buck DC converter for driving a load,where N=2n and N is an even number equal to or greater than 4 and n is apositive integer, the N-phase buck DC converter comprising: N storageinductors connected to the load, wherein the N storage inductors aredivided into a first part of storage inductors and a second part ofstorage inductors, the first part of storage inductors include a firststorage inductor to a (2n−1)^(th) storage inductor with a fixedinterval, the second part of storage inductors include a second storageinductor to a 2n^(th) storage inductor with the fixed interval; Nlow-side switches, wherein one side of each low-side switch is connectedto a corresponding one of each of the N storage inductors, respectively;a first input capacitor; a second input capacitor connected to the firstinput capacitor in series, wherein a contact of the first inputcapacitor and the second input capacitor is connected to the secondstorage inductor of the N storage inductors; N high-side switchesdivided into a first part of high-side switches and a second part ofhigh-side switches, wherein the first part of high-side switches includea first high-side switch to a (2n−1)^(th) high-side switch with thefixed interval, the second part of high-side switches include a secondhigh-side switch to a 2n^(th) high-side switch with the fixed interval,the (2n−1)^(th) high-side switch of the first part of high-side switchesis connected to the (2n−1)^(th) storage inductor of the N storageinductors; and N−2 clamping capacitors divided into a first part ofclamping capacitors and a second part of clamping capacitors, whereinthe first part of clamping capacitors include a first clamping capacitorto a (2n−3)^(th) clamping capacitor with the fixed interval, and oneside of a k^(th) clamping capacitor is connected to a k^(th) high-sideswitch and a (k+2)^(th) high-side switch, an other side of the k^(th)clamping capacitor is connected to a k^(th) storage inductor of the Nstorage inductors, wherein k is an odd number between 1 and (2n−3), thesecond part of clamping capacitors includes a second clamping capacitorto a (2n−2)^(th) clamping capacitor with the fixed interval, and oneside of a j^(th) clamping capacitor is connected to a j^(th) high-sideswitch and a (j+2)^(th) high-side switch, an other side of the j^(th)clamping capacitor is connected to a (j+2)^(th) storage inductor of theN storage inductors, wherein j is an even number between 2 and (2n−2).2. The N-phase buck DC converter according to claim 1, wherein in thefirst part of high-side switches, one side of the first high-side switchis connected to the first input capacitor, and the first high-sideswitch to the (2n−1)^(th) high-side switch are connected in seriessequentially.
 3. The N-phase buck DC converter according to claim 1,wherein in the second part of high-side switches, one side of the secondhigh-side switch is connected to the second input capacitor, and thesecond high-side switch to the 2n^(th) high-side switch are connected inseries sequentially.
 4. The N-phase buck DC converter according to claim1, wherein when a T^(th) high-side switch is turned on, the other (N−1)high-side switches are turned off, a corresponding T^(th) low-sideswitch is turned off, and the other (N−1) low-side switches are turnedon, wherein T is a positive integer between 1 and N.
 5. The N-phase buckDC converter according to claim 1, wherein when a T^(th) high-sideswitch is turned on, one input capacitor charges one of the clampingcapacitors and drives the load via the T^(th) high-side switch, or oneof the clamping capacitors discharges to drive the load.
 6. The N-phasebuck DC converter according to claim 1, wherein when the N high-sideswitches are all turned off, the load is driven by temporary power ofthe N storage inductors.
 7. An N-phase buck DC converter for driving aload, wherein N=2n+1 and N is an odd number equal to or greater than 3and n is a positive integer, the N-phase buck DC converter comprising: Nstorage inductors connected to the load, wherein the N storage inductorsare divided into a first part of storage inductors and a second part ofstorage inductors, the first part of storage inductors include a firststorage inductor to a (2n+1)^(th) storage inductor with an odd numberedinterval, the second part of storage inductors include a second storageinductor to a 2n^(th) storage inductor with an even numbered interval; Nlow-side switches, wherein one side of each low-side switch is connectedto a corresponding one of each of the N storage inductors, respectively;a first input capacitor; a second input capacitor connected to the firstinput capacitor in series, wherein a contact of the first inputcapacitor and the second input capacitor is connected to the secondstorage inductor of the N storage inductors; N high-side switches,divided into a first part of high-side switches and a second part ofhigh-side switches, wherein the first part of high-side switches includea first high-side switch to a (2n+1)^(th) high-side switch with the oddnumbered interval, the second part of high-side switches include asecond high-side switch to a 2n^(th) high-side switch with the evennumbered interval, the (2n+1)^(th) high-side switch of the first part ofhigh-side switches is connected to the (2n+1)^(th) storage inductor ofthe N storage inductors; and N−2 clamping capacitors, divided in to afirst part of clamping capacitors and a second part of clampingcapacitors, wherein the first part of clamping capacitors include afirst clamping capacitor to a (2n−1)^(th) clamping capacitor with theodd numbered interval, and one side of a k^(th) clamping capacitor isconnected to a k^(th) high-side switch and a (k+2)^(th) high-sideswitch, an other side of the k^(th) clamping capacitor is connected to ak^(th) storage inductor of the N storage inductors, wherein k is an oddnumber between 1 and (2n−1), and when N>3, the second part of clampingcapacitors include a second clamping capacitor to a (2n−2)^(th) clampingcapacitor with the even numbered interval, and one side of a j^(th)clamping capacitor is connected to a j^(th) high-side switch and a(j+2)^(th) high-side switch, an other side of the j^(th) clampingcapacitor is connected to a (j+2)^(th) storage inductor of the N storageinductors, wherein j is an even number between 2 and (2n−2).
 8. TheN-phase buck DC converter according to claim 7, wherein in the firstpart of high-side switches, one side of the first high-side switch isconnected to the first input capacitor, and the first high-side switchto the (2n−1)^(th) high-side switches are connected in seriessequentially.
 9. The N-phase buck DC converter according to claim 7,wherein in the second part of high-side switches, one side of the secondhigh-side switch is connected to the second input capacitor, and thesecond high-side switches to the 2n^(th) high-side switches areconnected in series sequentially.
 10. The N-phase buck DC converteraccording to claim 7, wherein when a T^(th) high-side switch is turnedon, the other (N−1) high-side switches are turned off, a correspondingT^(th) low-side switch is turned off, and the other (N−1) low-sideswitches are turned on, wherein T is a positive integer between 1 and N.11. The N-phase buck DC converter according to claim 7, wherein when aT^(th) high-side switch is turned on, one input capacitor charges one ofthe clamping capacitors via the T^(th) high-side switch and drives theload, or one of the clamping capacitors discharges to drive the load.12. The N-phase buck DC converter according to claim 7, wherein when theN high-side switches are all turned off, the load is driven by temporarypower of the N storage inductors.